![]() ![]() Blitter line mode with invalid settings (for example width not 2, octant and line direction mismatch etc) is now almost accurately emulated.Blitter timing is now cycle accurate (previously startup behavior and interrupt timing was not fully accurate).Audio interrupt timing is now cycle accurate (Was almost fully accurate previously).Serial port internal timing, interrupt timing, including SERDATR status bits are now cycle accurate (I used serial port interrupts as a timer in my cputester real 68000 interrupt timing tests).Timers were accurate previously but now also interrupt timing, TOD counting, CPU/E-clock sync, and more, including undocumented side-effects are cycle accurate. CIA emulation is now fully cycle accurate.Custom chipset interrupt timing is now cycle accurate.68000 emulation is finally fully cycle accurate, last missing part, interrupt level change detection timing, is now cycle accurate.New hardware emulation features and update ![]() Disk status/interrupt timing is not fully confirmed yet.Not all blitter line draw width != 2 (invalid line draw configuration, normally not used) conditions are 100% accurate.OCS and ECS Denise mid screen resolution changes are not pixel perfect, correct chip model specific bit pattern is not emulated yet.Lots of expected and unexpected hardware features found and implemented.įeatute updates that got delayed but will be implemented in 5.0 Big thanks to ross for writing test programs that required perfect cycle accuracy.68000 based unexpanded (with optional Slow or Fast RAM expansion) configurations are now 100% cycle-accurate. ![]()
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